The present invention relates to a semiconductor device and to a fabrication method therefor. Moreover, the present invention relates to a substrate arrangement for driving a flat-plate light valve used for a direct-view display device and a projection-type display device.
More specifically, the present invention relates to a semiconductor integrated circuit substrate arrangement in which a group of pixel electrodes, a group of switches, and a group of driving circuit elements are formed on a single-crystal semiconductor silicon film on at electrical insulator. The substrate arrangement is integrated with, for example, a liquid crystal panel to constitute the so-called active-matrix arrangement.
Particularly, the present invention relates to a semiconductor device having a structure effective for minimizing the generation of heat in the semiconductor device or preventing the temperature of the semiconductor device from rising by releasing the heat from the semiconductor device when heat is generated.
An existing active-matrix arrangement is made by forming amorphous silicon or polycrystalline silicon on an electrical insulator such as a transparent glass substrate or transparent quartz substrate and further forming some or all of a group of picture element electrodes, a group of switching elements, and a group of driving circuit elements on the amorphous or polycrystalline silicon. However, it is not yet been successfully attempted to form all of the picture element group, switching element group, and driving circuit group on a single-crystal semiconductor film over an electrical insulator.
The substrate in which a semiconductor such as silicon is formed on an electrically insulating film is commonly called SOI (Silicon On Insulator), which is now recognized as a semiconductor device structure having a high operation speed and high integration density.
FIG. 2 shows a sectional view of a wafer having the SOI structure. In FIG. 2, reference symbol 21 is a single-crystal silicon substrate with a thickness of 500 to 1000 microns, 22 is a silicon oxide film with a thickness of over hundred angstroms to several microns, 23 is a single-crystal silicon film with a thickness of one hundred angstroms to several microns.
For a semiconductor integrated circuit made of an SOI wafer, the single-crystal silicon layer 23 on the electrical insulating film 22 is very thin. Therefore, when the integrated circuit comprises a complementary MIS transistor (complementary metal-insulator-semiconductor transistor; hereafter referred to as complementary MIS Tr), there are advantages that electric capacities between source and substrate, between drain and substrate, and between gate and substrate are decreased, the operation speed of the integrated circuit can be increased, a device isolation region between transistors can be formed very small, and the integration density can be increased as compared to when the integrated circuit is formed on a bulk single-crystal silicon wafer because the electric insulator 22 is present.
FIGS. 3(a) to 3(d) show a method for making single-crystal silicon on an existing insulating film using a method of bonding a single-crystal silicon layer with an oxidized single-crystal silicon layer.
In FIG. 3(a), bulk single-crystal silicon 301 is thermally oxidized to form a silicon oxide SiO.sub.2 layer 302.
In FIGS. 3(b) and 3(c), the silicon with SiO.sub.2 prepared in FIG. 3(a) is bonded with the single-crystal silicon 303 at a high temperature.
In FIG. 3(d), the thickness of the silicon 301 on whose surface SiO.sub.2 is formed is decreased up to several microns or less through grinding or etching.
As shown in FIG. 3(d), conventional SOI generally has a structure in which an SiO.sub.2 layer 302 is present between thick single-crystal silicon 303 and thin single-crystal silicon 301.
For an SOI wafer, because the insulating film 302 is present just under the thin single-crystal silicon 301 on which an integrated circuit is formed, the heat generated by the current flowing when the integrated circuit operates is not released to the thick conductive single-crystal silicon 303 under the insulating film 302 but it is collected in the thin single-crystal silicon layer 301 and serves to raise the temperature of the thin single-crystal silicon layer with the passage of time.
When the integrated circuit comprises a complementary MIS Tr, the current flowing through the transistor increases and the temperature elevation rate also increases if the transistor size is decreased to increase the integration density.
If the temperature of thin single-crystal silicon layer rises, carrier trap levels are easily generated in a gate insulator of the MIS transistor, causing transistor characteristic fluctuation, and degrading the integrated circuit reliability.
FIG. 4 is a sectional view showing another embodiment of a semiconductor device. The sectional view in FIG. 4 shows an N-type metal-oxide semiconductor field-effect transistor (hereafter referred to as MOS Tr) formed on poycrystalline silicon (hereafter referred to as Poly-Si) on an insulating substrate.
Reference numeral 401 is a transparent substrate made of glass or quartz, 402 and 403 are a source and drain containing N-type impurities at a high concentration of approx. 1.times.10.sup.19 to 1.times.10.sup.20 cm.sup.-3 respectively, and 404 is a P-well region containing little or few impurites or containing impurities at a low concentration of about 1.times.10.sup.16 cm.sup.-3.
The source 402, drain 403, and P-well 404 are formed in Poly-Si. Symbols 405 and 406 are silicon oxide SiO.sub.2 formed by oxidizing Poly-Si containing the source 402, drain 403, and P-well 404. The SiO.sub.2 405 of these two silicon oxide films SiO.sub.2 serves as a gate insulator of an N-type MOS Tr.
Symbol 407 is Poly-Si containing N-type impurities at a high concentration of approx. 1.times.10.sup.20 cm.sup.-3, which serves as a gate of a MOS Tr. An N-type MOS Tr comprises the source 402, drain 403, P-well 404, gate insulator 405, and gate, 407. Symbol 408 is an intermediate insulating film formed by depositing a silicon oxide, 409 is a source electrode made of aluminum, and 410 is a drain electrode made of aluminum. The intermediate insulating film 408 is removed from portions where the source electrode 409 contacts the source 402 and the drain electrode 410 contacts the drain 403. Symbol 411 is a passivation film made of a silicon nitride film or silicon oxide.
Also for an existing semiconductor having the sectional structure shown in FIG. 4, the transparent insulating substrate 401 under the N-type MOS Tr is an insulator and the intermediate insulating film 408 and the passivation film 411 above the N-type MOS Tr are insulating films. Therefore, the heat produced when current flows through the N-type MOS Tr formed in Poly-Si is hardly released from the Poly-Si.
For the structure of a transistor made of amorphous silicon (hereafter referred to as a-Si) formed on the transparent insulating substrate mainly used for a display device though not illustrated, an insulating substrate is present under the transistor and an insulating film such as a passivation film is present above it. Therefore, the heat generated when a current flows through the transistor is not released from the transistor but it is easily collected in the transistor.
In recent years, the size of a transistor (hereafter referred to as Tr) constituting an integrated circuit formed on single-crystal silicon has been continually decreased. For example, when the integrated circuit comprises a complementary metal-oxide-semiconductor transistor (hereafter referred to as CMOS Tr), the length of the Tr is already decreased to 1 .mu.m or less, and moreover a length of 0.2 to 0.3 .mu.m has recently been realized.
FIG. 5 shows a sectional view of a semiconductor which is a sectional view of an N-type MOS Tr formed in single-crystal silicon.
Reference numeral 501 is a single-crystal silicon layer containing P-type impurities at a low concentration of approx. 1.times.10.sup.16 cm.sup.-3, 502 and 503 are a source and drain containing N-type impurities at a high concentration of approx. 1.times.10.sup.20 cm.sup.-3 respectively, 504 is a gate insulator, 505 is a gate made of Poly-Si containing N-type impurities at a high concentration of approx. 1.times.10.sup.20 cm.sup.-3, 506 is an intermediate insulator made of a silicon oxide for preventing the gate 505 and aluminum wires 507 and 508 from shorting, 507 is an aluminum layer electrically connected to the source 502, 508 is an aluminum layer electrically connected to the drain 503, and 509 is a passivation film made of, for example, a silicon nitride film. In FIG. 5, the N-type MOS Tr comprises the single-crystal silicon layer 501, source 502, drain 503, gate insulating film 504, and gate 505.
As the length L of the gate 505 decreases to 0.5 .mu.m or less, the current flowing between the source 502 and drain 503 increases. As a result, the temperature of the single-crystal silicon layer 501 rises. The heat produced in the N-type MOS Tr is also transmitted to the aluminum layers 507 and 508 because the source 502 and drain 503 are electrically connected to the aluminum layers 507 and 508. However, because the existing passivation film on the aluminum layers is made of a silicon nitride film or silicon oxide which is inferior in thermal conductivity, the heat transmitted to the aluminum layers 507 and 508 is not released outside the passivation film and therefore, the temperature of the region where Tr is formed rises.
Thus, when the transistor size decreases, the current flowing through the transistor increases. Therefore, the current flowing through the entire integrated circuit is very large compared with the existing current. As a result, the heat produced in the integrated circuit increases and the temperature of the integrated circuit rises. If the temperature of the single-crystal silicon layer where the integrated circuit is formed rises, carrier trap-levels are easily generated in the gate insulator of the MOS Tr, the transistor characteristic fluctuates, and the integrated circuit reliability is degraded.
Moreover, a semiconductor substrate and a semiconductor for a light valve are already known in which a single-crystal silicon thin film device forming layer is formed on an insulating support substrate through an adhesive layer and an insulating layer is formed on the single-crystal silicon thin film device forming layer, respectively.
When a transistor formed on single-crystal silicon on an insulating substrate is operated for an extended time, that is, when current flows through the Tr for a long time, the temperature of the single-crystal silicon where the current flows rises due to the heat produced due to flowing of the current. When the temperature of an electrical insulator or thin single-crystal silicon film rises, the heat is not released and the temperature continuously rises as long as current flows because single-crystal silicon is thin and the thin single-crystal silicon is surrounded by electrical insulators and air.
A MOS Tr which is the most popular type of MIS Tr is described below for ease of understanding. Every reference to a MOS Tr below is also applicable to the MIS Tr in general.
FIG. 6 shows a sectional view of a MOS Tr formed on a substrate in which a thin single-crystal silicon layer 602 with a thickness of 0.1 to several microns is formed on a quartz layer 601 with a thickness of several hundreds of microns to 1000 microns. Reference numerals 603 and 604 are source and drain of the MOS Tr, 605 is a well region, 606 is a gate oxide, and 607 is a gate made of Poly-Si. Reference numeral 608 is a channel serving as a current path of the MOS Tr. Though omitted in FIG. 6, the upper portions of the source 603, drain 604 and gate 607 are covered with an insulator such as a silicon oxide or silicon nitride film. Quartz serving as an electrical insulator is also present under the thin single-crystal silicon layer 602. Therefore, when current flows through the channel 608 serving as a current path and heat is produced, the heat of the channel 608 is barely released and the temperature proximate the channel 608 is raised since the upper portion of the channel 608 is surrounded by the electrical insulating film such as a silicon oxide film or a silicon nitride film and the insulator of the quartz 601 under the single-crystal silicon layer 602.
FIG. 7 shows another sectional view of the MOS Tr formed on a single-crystal silicon layer on an electrical insulator. Symbol 701 is a silicon oxide with a thickness of over thousand angstroms to several .mu.m and 702 is a thin single-crystal silicon layer with a thickness of 1 to several microns. The MOS Tr is formed by forming a well 703, source 704 and drain 705 in the thin single-crystal silicon layer 702 and also forming a gate 707 comprising a gate oxide 706 and a Poly-Si layer deposited thereon.
Reference numerals 709 denotes an interlayer insulating film made of silicon oxide and 710 is aluminum metalization which is connected to the source 704 and drain 705 separately. Reference numeral 711 is a passivation film made of a silicon nitride film, 712 is an adhesive with a thickness of several .mu.m, and 713 is a glass substrate with a thickness of over hundred to 1000 .mu.m.
Also in FIG. 7, when current flows through a channel 708 serving as a current path of the MOS Tr, the heat produced in the channel due to flowing of the current is hardly released and thereby the channel temperature rises because the lower portion of the thin single-crystal silicon layer 702 is surrounded by the silicon oxide 701 and the upper portion of it is surrounded by the silicon oxide 709 and passivation film 711 and moreover by insulators such as the adhesive 712 and glass substrate 713.
For a semiconductor for a light valve substrate on which a group of pixel switching transistors (hereafter referred to as Sw-Tr group) for selectively supplying electric power to a pixel electrode and a driving circuit for driving the pixel Sw-Tr group are formed, a high voltage of approx. 15 V is applied to the gate electrode and drain electrode of a pixel Sw-Tr to selectively operate the Sw-Tr when the Sw-Tr comprises a MOS Tr.
In this case, a very large current flows through a MOS Tr formed on single-crystal silicon independently of whether the MOS Tr is a P-type or N-type MOS Tr. Therefore, the channel section of the Sw-Tr formed on the thin single-crystal silicon on the electrical insulator has a high temperature.
FIG. 8 shows a sectional view of an N-type MOS Tr formed on a thin single-crystal silicon layer 802 on an electrical insulator 801. Symbol 801 is a silicon oxide with a thickness of 0.1 to several .mu.m, 802 is a thin single-crystal silicon layer with a thickness of 0.1 to 2 microns, 803 is a p-well, and 804 and 805 are source and drain regions, respectively. Symbol 806 is a gate insulator made of a silicon oxide and 807 is a gate made of Poly-Si. Symbol 808 is a channel serving as a current path of the MOS Tr.
In FIG. 8, the source 804 is grounded and a high voltage of 15 V is applied to the drain 805 and the gate 807. In this case, because the gate 807 and drain 805 have the same potential, no electric field is generated between the gate and drain at the both sides of the gate insulator 806. However, an intense electric field is applied to the gate insulator close to the source. Another problem is caused by the two events of high temperature and intense electric field. That is, excessive trap levels for capturing carriers flowing through the channel 808 are generated in the vicinity of the source 804. Because many flowing carriers are captured by these traps, a problem occurs in that the threshold voltage (gate voltage when current starts flowing between source and drain; hereafter referred to as Vt) of the N-type MOS Tr slowly rises while current flows. For an N-type MOS Tr, flowing carriers are electrons and carriers captured by traps are also electrons. For a P-type MOS Tr, flowing carriers are holes and carriers captured by traps are also holes. Therefore, Vt of the P-type MOS Tr fluctuates in the direction in which the absolute value of Vt increases. This is because, when flowing carriers are captured by traps of a gate insulator, a gate voltage with a high absolute value is required to form a channel, that is, to invert a well layer just under the gate insulator 806.
For the semiconductor device for a light valve substrate, the voltage to be applied to the Sw-Tr group of a pixel section requires a high voltage of 10 V or higher, for example, 15 V, in order to drive a liquid crystal. However, the voltage to be applied to most transistors of a driving circuit section is a relatively low voltage of 5 V or lower. In this case, the intensity of the electric field applied between the gate and source of most transistors constituting the driving circuit is approx. 1/3 as low as that of the electric field applied between the gate and source of the Sw-Tr of the pixel section.
The number of trap levels of carriers generated in a gate insulator, as described above, relates to a high temperature of the channel section and the intensity of an electric field between a gate and source. A large number of trap levels are not generated by only one of these two factors, such as, for example, only the high temperature of the channel section. The density of traps generated in the gate insulator increases as the temperature of the channel section gets higher and the intensity of the electric field between the gate and source gets higher.
Therefore, most transistors with a low intensity of the electric field between a gate and source do not have so many trap levels in the gate insulator or very large Vt fluctuation of the transistors.
In a semiconductor device for a light valve arrangement in which a pixel Sw-Tr group for selectively supplying electric power to pixel electrodes and a driving circuit for driving the pixel Sw-Tr group are formed on single-crystal silicon thin film disposed on an electrical insulator, some of the transistors constituting the driving circuit and all of the Sw-Tr's of the pixel section are main transistors having Vt fluctuations when a high-intensity electric field is applied between a gate and drain, a large current flows through a channel, the channel temperature rises, a high-intensity electric field is applied between a gate and source, and carrier trap levels are generated in a gate oxide.
It is an object of the present invention to minimize the Vt fluctuation of a pixel Sw-Tr in which a high voltage is applied to the gate and drain of a semiconductor device for a light valve device in which a pixel Sw-Tr group for selectively supply electric power to pixel electrodes and a driving circuit for driving the pixel Sw-Tr group are formed on a thin single-crystal silicon layer on the above electrical insulator.
Though it has been attempted by applicants to form a shading film so that no incident light strikes a pixel Sw-Tr, some of the light penetrates around the shading film to irradiate the pixel Sw-Tr in most cases. Carriers generated due to light are the cause of a leakage current.
It is therefore also an object of the present invention to control the Vt fluctuation of the pixel Sw-Tr and to decrease the leakage current due to incident light.
The present invention provides a semiconductor device with a high reliability such as an integrated circuit or display device by preventing the temperature rise of a single-crystal silicon thin film formed on which is an integrated circuit comprising a miniaturized Tr described above, or which is part of an SOI wafer, and also by preventing the temperature of Poly-Si formed on an insulating substrate, or a transistor formed in a-Si from rising.
Moreover, it has been found that the conventional semiconductor substrate and the semiconductor substrate for a light valve having a structure shown in FIG. 9 also have a problem in that the Vt of a MOS transistor increases due to the operation of the MOS transistor when the MOS transistor is formed on a single-crystal silicon thin-film device forming layer.
In FIG. 9, symbol 901 is a single-crystal silicon thin-film device forming layer, 902 is an insulating layer, 903 is an adhesive layer and 904 is an insulating support substrate. Concerning the above problem, because one surface of the single-crystal silicon thin-film device forming layer 901 contacts the thick insulating support substrate 904 with a low heat conductivity through the adhesive layer 903 and the other surface of the layer 901 contacts the air with a low heat conductivity through the insulating layer 902 in the semiconductor substrate and the semiconductor for a light valve having the structure shown in FIG. 9, the heat produced due to the operation of a MOS transistor is stored in the single-crystal silicon thin-film device forming layer and many carriers are deeply trapped into the gate insulator of the MOS transistor, and the Vt of the MOS transistor is therefore increased.
To solve the above problem, it is effective to quickly release the heat produced due to the operation of the MOS transistor without storing it in the single-crystal silicon thin-film device forming layer.
It is an object of the present invention to provide a semiconductor substrate and in particular, a semiconductor substrate for a light valve for solving the above problem, preventing the threshold value of the MOS transistor from increasing, and forming a MOS integrated circuit superior in reliability.
The problems to be solved by the present invention described above are summarized below.
(1) To minimize the Vt fluctuation of a pixel Sw-Tr of a semiconductor device for a light valve substrate in which a pixel Sw-Tr group for selectively supplying electric power to pixel electrodes and a driving circuit for driving the pixel Sw-Tr group are formed on a thin single-crystal silicon layer on an electrical insulator. PA0 (2) To minimize leakage current due to light of the Sw-Tr. PA0 (3) To prevent the temperature of single-crystal silicon, Poly-Si, and a-Si from rising due to the heat produced by the operation of Tr's formed in the single-crystal silicon, Poly-Si, and a-Si on an electrical insulator. PA0 (4) To prevent the temperature of single-crystal silicon from rising due to the heat produced by the operation of a miniaturized Tr in single-crystal silicon. PA0 (5) To release the heat produced in a single-crystal silicon thin-film device layer in a semiconductor substrate, and in particular, a semiconductor substrate for a light valve, having an insulating layer on a single-crystal silicon thin-film device forming layer through an adhesive layer on an insulating support substrate. PA0 &lt;1&gt; The length of a pixel Sw-Tr comprising a MOS Tr is larger than the minimum gate length among the gate lengths of many MOS Tr's forming a driving circuit. PA0 &lt;2&gt; The pixel Sw-Tr comprises a double drain structure (LDD structure: Lightly Doped Drain structure) in which the impurity concentrations of the source and drain decrease at the side close to a channel and increases at the side far from the channel. PA0 &lt;1&gt; To form integrated circuits in single-crystal silicon, some of the circuits are formed in a region for easily releasing heat, that is, a single-crystal silicon region where no electrical insulator is embedded and other circuits consuming less power, having a low operation frequency, or requiring a high operation speed are formed on an electrical insulator or in a single-crystal silicon layer. PA0 &lt;2&gt; For a semiconductor film (single-crystal silicon, Poly-Si, or a-Si) on an insulator, an insulating film is formed with an aluminum nitride (AlN) layer or a multiple layer of an aluminum nitride layer and other insulating film. Moreover, the thin semiconductor film is made to contact the aluminum nitride layer at a portion of the thin semiconductor film. Or, metallic wiring made of Poly-Si in the integrated circuit formed on the thin semiconductor film layer is made to locally contact the aluminum nitride layer.